Digital noise generator circuit

Digital noise is a time random process, it is very similar to physical noise, and it's called pseudorandom process. A digital sequence of binary digits is called pseudorandom sequence, it is a sequence of pulses of pseudorandom length, and delays between this pulses is pseudorandom. A period of repetition of this sequence is much longer than maximum duration of time between pulses.

In most cases to produce a pseudorandom sequence is used so-called "M - sequence" (Maximum length sequence), its design can be based on shift registers, and modulo 2 adders in the feedback path.

The circuit diagram of digital noise generator is shown in Fig. 1. This circuit produces a noise signal with uniform spectral density in the working frequency range.

Digital noise generator circuit diagram with CMOS IC

Fig. 1. Circuit diagram of digital noise generator, DD1 - CD4030, DD2 - CD4015, the power supply is a 9V battery.

This digital noise generator circuit is composed of a serial 8-bit shift register CD4015, a modulo 2 adder (DD1.3), a clock oscillator circuit (DD1.1 and DD1.2), and a startup circuit (DD1.4), where DD1 is IC CD4030 (it comprises 4 quad exclusive - OR gates).

The clock generator is based on gates DD1.1 and DD1.2. The gate DD1.1 is used as a buffer, the gate DD1.2 works as an inverter. The repeating frequency of pulses is about 35 kHz. The pulses form the output of the clock generator goes to the clock inputs "C" of shift registers DD2.1 and DD2.2. The serial connection of shift registers forms an 8-bit shift register. To write the data to the shift register, the inputs "D" is used. From gate DD1.3 (the modulo 2 adder in the feedback path) the signal goes to the input "D" of the register DD2.1.

Signals of the clock generator and digital noise generator

Fig. 2. Signals of the clock generator V(gen) and output V(out) of the digital noise generator.

There is a state of the shift register, where all outputs are low. It can be happened at startup. This is a forbidden state for M - sequence, in this sequence all-zero state is not allowed, because in case it happened, the data shifting will be halted. To avoid this situation, in the circuit is used an initiation circuit, based on logic gate DD1.4. When the power supply is applied to the main circuit, the initiation circuit produces a short pulse on its output, so the shift register changes its state, and now there is at least one output is high. After that, the initiation circuit doesn't affect the main circuit.

LTSpice model of the digital noise generator

Fig. 3. LTSpice model of the digital noise generator. Download this LTSpice model. Also you'll need CD4000 library.

The pseudorandom signal (see Fig. 2) can be obtained from any output of the shift register, in this circuit the output signal is taken from the last output of DD2.2. The circuit can be powered from 3..9 V power supply.

The pseudorandom signal from the output (with the voltage divider 100K+4K) was recorded in the MP3 file, and it can be heard below:

LTSpice model of this circuit (see Fig. 3) can be downloaded here: Download digital_noise_generator_circuit.asc