This digital sine wave generator provides a very good accuracy for a sine wave synthesis. If the input signal is formed using a crystal oscillator, the output sine wave signal will have the same accuracy as the input signal.

So, we can say that this circuit (see Fig.1.) provides conversion of the pulse signal into sine wave signal. The circuit uses two presettable "divide-by-N" counters DD1 and DD2 (CD4018) and one connected as an inverter 2-input NAND logic gate DD3.1 (CD4011).

Fig.1. Circuit diagram of the digital sine wave generator.

DD1, DD2 - CD4018; DD3 - CD4011 (or CD4001)

The circuit divides the input frequency (10 kHz) by 20, therefore the output frequency is 500 Hz. The input frequency may vary, for the other input frequency value match the capacitor C1 value. The maximum input frequency is 3 MHz (it depends on the IC manufacturer) with supply voltage of 5 V.

Let's see how the circuit works. Each counter DD1 and DD2 are based on the five Johnson counter stages connected in series. All outputs of this counters are inverted. Because of this, the logic gate DD3 is used as the inverter to invert the signal from the output of the last counter of DD1 to the data input D0 of DD2 (the two inversion functions will "cancel" each other out). This logic gate DD3 connects two IC in series, so there is total 10 Johnson counters are used. The signal from the last output of the second IC DD2 goes back do the data input D0 of DD1. It creates the necessary feedback loop to compose a circular shift register.

Let's imagine all the Johnson counters are set to a logic level of "1", so there is a logic level of "0" on all their outputs (keep in mind all outputs are inverted). It means that the data input D0 of the DD1 has a "low" logic level too. And now, with each pulse on clock inputs of DD1, DD2, the outputs will change their state step-by-step to a "high" logic level. At the end, there will be a "high" logic level on the last output and, respectively, the same "high" logic level will appear at the data input D0 of the DD1. And now with each pulse all outputs will set to the "high" logic level, and so on and on over and over again. It forms this pattern:

000000000 100000000 110000000 111000000 111100000 111110000 111111000 111111100 111111110 111111111 111111111 011111111 001111111 000111111 000011111 000001111 000000111 000000011 000000001 000000000

Note that in this sequence states "All high" and "All low" are twice, they form bottom and top parts of the sine wave (see Fig. 2.).

Fig. 2. Input pulses and output stair shaped signal without the capacitor C1.

The resistors R1..R9 are connected to the outputs of the all CD4018, this creates a stair shaped signal in the point where all resistors are connected together. But because of the capacitor C1 that is the part of the integrator circuit, the output signal is smoothed and it has a sine wave shape. So, all this is works as a digital to analog converter (DAC).

Because all resistors R1..R9 are the same value and they are connected to the same point, they can be replaced by a single in line (SIL) resistor package. By the way, it is not necessary that the value of the resistor package is 20 Kilohms, the value may be another, for, example, 30 Kilohms.