The schematic diagram shown in Figure 1 have the ability to synthesize a sinusoidal waveform with a frequency of 0.01 Hz to 1 MHz. The clock signal feeds to the input of the binary counter IC1, this clock frequency is 32 times more than the output sinusoidal signal. The outputs Q0...Q3 of the counter IC1 are connected through the logic gates XOR IC2 to the resistors R1...R4, the total current through this resistors is summed at the input of the operational amplifier IC3. When the output Q4 of the binary counter IC1 goes low, the logic gates DD2 works as buffers, and when the same output Q4 goes high, then the logic gates DD2 works as inverters (see Fig. 3). The logic level at the output Q4 is changed every 16 clock pulses (or every 8 clock pulses at the output Q0 of the counter IC1). Thus, this creates the positive and negative halves of the sine-wave form. So the period consists of 2^{5}=32 parts.

Fig.1.

IC1 - CD4040, IC2 - CD4030, IC3 - OP77

Fig. 2.

Download LTSpice model of the Digital Sine Wave Oscillator (you'll need CD4000 library).

Fig. 3.

Because the sinusoidal signal at the output has a staircase form, then to get the sine wave of the signal it should be smoothed by integration, this can be done by connecting a capacitor across the resistor R5. The value of the capacitor depends on the operating frequency and can be found by the formula:

**C=1/(16*F _{out}*R5)**

where C - the capacitance of the integrating capacitor, μF;

F

R5 - the resistance of the resistor R5, ohms (2200).

Hobby Elektronika 1999 №11