FM detector circuit

This detector for frequency modulation has been described in the "Radio" magazine of 1983, N 10, by Yakov Lapovok, UA1FA. The detector circuit is based on 3 NOR gates of 74 series.

Let's see how this FM detector works. The input frequency modulated signal is fed to the pulse forming network R1V1D1, then goes further to the gate D3 and to the inverter D2. If the output of D1 is low, the capacitor C2 charges slowly through the input resistance of the gate D3. If the output of D1 is high, the capacitor C2 discharges by the gate D2 through the diode V2. Therefore, from the output of the gate D1 the pulse leading-edge is fed to the upper input of the gate D3, the pulse is delayed just a little bit relative to the pulse at the other input of the gate D3.

FM detector circuit diagram

Figure 1
D1-D3 - 7402; V1, V2 - D9B (a germanium USSR diode);
C1 - 0.1 μF; R1 - 1k;
C2 - 50...150 pF (match the value) for the IF of 500 kHz.

The pulse width at the output of the FM detector is proportional to the leading-edge delay, and the direct current is proportional to modulated signal.

The value of the capacitor C2 is 50...150 pF for the intermediate frequency of 500 kHz. Its value should be matched to get the maximum output voltage.

The FM detector circuit has been simulated using LTSpice program (see Fig. 2.). Note the diode D3 - it is a protective diode in the real IC 7402. The network D4R2 emulate the input impedance of the real 7402 gate. These components has been added to the simulation to make the model of 7402 IC more realistic. The low-pass filter are composed of R3C3.

FM detector circuit simulated using LTSpice program

Figure 2

The LTSpice simulation model of this frequency modulation detector is here: fm_detector_circuit.asc, it requires the 74HC library: