Frequency comparator circuit based on digital IC's

This frequency comparator circuit (see Fig. 1.) can detect whether an input frequency is higher or lower than some value. If it is higher, then the output of the circuit is high, otherwise it is low.

An input signal should have a duty cycle close to 50%, so the second half of trigger DD2 can be used as a divider by 2, connected at input of the circuit to get necessary duty cycle value.

Frequency comparator circuit based on IC 74123 and 7474

Fig. 1. DD1 - 74123, DD2 - 7474

The IC DD1 74HC123 is a monostable multivibrator with reset, it produces a short positive pulse when a negative edge appears at A input. The IC DD2 is a D - flip-flop, it used as a memory cell, a rising edge on its clock input captures a value at D input. If a half-period of input signal is less then the width of positive pulse produced by monostable multivibrator, then the signal at D input is high, so the output of D - flip-flop is high (see Fig. 2), in other case the output of D - flip-flop is low.

The IC DD1 74HC123 can be replaced with 74HC121 or 74121, but in this case pins A1 and A2 of IC 74121 should be grounded, pin B should be using for the input.

Oscillogram of the frequency comparator circuit

Fig. 2.

The network R1C1 determines a pulse width, so T = 0.45*R1*C1 (for 74HC123, VDD = 5V). For an input frequency F the pulse width should be about 0.5/F, and the pulse width is T ≈ R1*C1, F = 1/(R1C1).
For example, if F = 5 kHz, C1 = 10nF, R1 = 1/(F*C1) = 1/(5000*10*10^-9) = 20000 = 20K.

frequency comparator circuit based on IC 4000

Fig. 3.

In this circuit is used TTL IC's of 74 or 74HC series, but the circuit can be designed using CMOS IC's of 4000 series (see Fig. 3). In this circuit the monostable multivibrator is based on gates DD1.1 and D2.2, it produces a short negative pulse when a negative edge appears at the circuit input (see Fig. 4). Because the pulse is negative, the inverted output of D - flip-flop DD2 is used for output.

Signals of the frequency comparator circuit

Fig. 4.

The pulse width calculation is almost the same as in the previous circuit with 74 series, except the coefficient is 0.75, so
for F = 100 Hz, C1 = 0.2μF, R1 = 0.75/(F*C1) = 0.75/(100*0.2*10^-6) = 37500 ≈ 38K.

In both circuits a potentiometer can be used, connected in series with resistor R1, it will allow to adjust the pulse width, so the circuit can be tuned for desirable frequency.

Using LTSpice with CD4000

Fig. 5.

LTSpice models of this frequency comparator circuit can be downloaded here. In the model of circuit based on CMOS 4000 series (file frequency_comparator_circuit.asc) is used two diodes D1 and D2. It is necessary because logic gates in program LTSpice are almost ideal, but real gates comprises protection diodes. Without this diodes (especially without diode D2) the capacitor C1 couldn't be discharged fast enough.

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