This circuit (see fig. 1.) provides frequency division with a variable ratio, and it doesn't use any digital counters, shift registers or any other complicated integrated circuits. The circuit uses only one IC CD4001, one variable resistor and one capacitor.
Fig. 1. Frequency divider circuit with a variable division ratio based on NOR gates
Fin = 1 KHz, DD1 - CD4001
The base part of this circuit is a monostable multivibrator (see fig. 2.). It is called a "one-shot pulse generator" circuit. With a pulse on its input this circuit generates a wider pulse on its output. The output pulse width depends on the time constant R1C1. By changing variable resistor R1 value we can change the output pulse width.
Fig. 2. One-shot pulse generator circuit.
DD1 - CD4001 (quad 2-input NOR gates)
Let's see how this one-shot pulse generator (fig. 2.) works. We should note that the NOR gate DD1.1 has a high logic level at its output only if both its inputs are low, in all other cases there will be a low logic level.
The gate DD1.3 works as an inverter, its output connected to the upper input of the DD1.3 gate, it provides a feedback loop.
The high logic level is set at the inputs of the inverter DD1.3 through the variable resistor R1. Because of this, the output of this gate is low. If there is no pulses, both inputs of DD1.1 are low, it means that its output is high and the capacitor C1 is not charged.
Now, if a pulse appears on the lower input of DD1.1 gate, it will produce a negative pulse on its output. The capacitor C1 starts to charge through resistor R1, but at the beginning, while the capacitor is not charged yet, the negative pulse will pass through the capacitor to the inputs of the inverter DD1.3, so the positive pulse is applied through the feedback loop to the upper input of the DD1.1 gate. Now both inputs of the DD1.1 are low, and when the input pulse will gone, the circuit will provide high logic level on its output until the capacitor C1 is charged. It will take a time determined by the R1C1 network. When the capacitor C1 is charged, the circuit resets, and the capacitor C1 starts to discharge through the resistor R1 and through (it's more important!) the inputs of the gate DD1.3.
The real integrated circuit CD4001 has protective diodes and resistors on all inputs (see Fig 3.).
Fig. 3. The input of a CMOS IC protected with diodes from damage due to electrostatic discharge
So the capacitor C1 will discharge across the upper protective diode, it will happen quite fast.
Let's get back to the circuit diagram shown in Fig 1. Now we know that the wide pulse appears on the output of DD1.3 gate. This wide pulse blocks input pulses from passing to the circuit output. The number of blocked input pulses plus one is equal to the division ratio of the circuit. The accuracy of the circuit depends only on the accuracy of input frequency.
In that circuit we can use IC CD4011 instead of CD4001, but it takes some changes in the schematic (see Fig .4.).
Fig. 4. Frequency divider circuit with a variable division ratio based on NAND gates
Fin = 1 KHz, DD1 - CD4011
As we can see here, the circuit provides negative pulses, because the monostable multivibrator based on the gates DD1.2, DD1.3 generates a negative wide pulse. The variable resistor R1 connected between inputs of DD1.3 and the ground. The circuit works the same way as the circuit from the Figure 1.
OK, but if we want to simulate any of this circuits in the LTSpice program, then we should consider that the LTSpice models of CD4000 series IC do not include protective diodes, so the capacitor C1 can't be discharged fast enough and circuits wouldn't work as it meant to be. To fix that, we can add diodes D1, D2 to the schematic (see Fig. 5.).
Fig. 5. Frequency divider circuit with a variable division ratio modified for the LTSpice program
Actually, only the diode D1 is important in this circuit.
Now the circuit works fine. You can download both circuits from Fig. 1 and Fig. 4.: CD4001.asc and CD4011.asc, you'll need CD4000 library.