Radio 1998, 10
The sine wave signal can be synthesized by digital way with shift register and a low-pass filter, the upper limit of the frequency is limited to 100 kHz.
The circuit diagram of the generator is shown in Fig. 1. It uses a shift register DD2, the signals from the eight outputs of the register is summing in the matrix of resistors R2..R9. The clock frequency of an oscillator is applied through the inverter DD1.1 to the clock input C of the IC DD2. The feedback from the output Q7 to the input D of IC DD2 passing through the inverter DD1.2. This feedback switches the logic level on all outputs of the IC DD2 after the eight clock pulses passing (see Fig. 2).
DD1 - 4093, DD2 - 74HC4094, DA1 - LM741
While 16 of the clock pulse is passing, the output voltage varies from minimum to maximum (during the first eight pulses) and returned to initial state (during the next eight pulses). Then the process repeats. Thus, the output frequency of the periodic oscillations is 16 times lower than the clock frequency.
Figure 2. Signals at pins of the IC DD2
The signal at the output of the summing matrix has step form. The weight of each part of the "step" is defined by resistance of resistors R2...R9, so you may need to regulate the circuit by selecting the values of R2...R9 to make all "steps" equal. This will creates a output sine wave signal with minimal distortion.
The components of R2-R9, R10, R12 not only works as summarizing matrix, but with the resistor R11 and capacitor C3 it works as the low-pass filter, converting a step voltage at the input of the op-amp (IC DA1) into the form of a sine wave signal.
The values of capacitor C3 for low-pass filter are shown in the table below.
|Cutoff frequency, Hz||10||102||103||104||105|
|Capacitance C3, uF||100||10||1||0.1||0.01|
Cyfrowy generator sygnalu sinusoidalnego.
1997, №11, p. 42, 43