Radio, 1987, №2
This voltage controlled frequency divider circuit (see figure in text) produces pulses of lower frequency that depends on the control voltage, and front edges of input and output pulses are synchronous. Actually, in this type of frequency dividers are used a monostable circuit, connected between an inverted output and D-input of D-flip-flop DD1, but in this design the monostable circuit is replaced with an adjustable delay circuit. The adjustable delay circuit comprises a current mirror circuit, based on transistors VT2, VT3, and capacitor C1. A current through transistor VT3 is controlled by voltage Uctr < U/2, so a current of the same value goes to the second branch of the current mirror circuit. This current charges the capacitor C1. Therefore, the rate of charging depends on the voltage Uctr.
How this frequency divider circuit works. In the initial state, the direct output of D-flip-flop DD1 is "on", so the capacitor C1 is discharged by transistor VT4. In the same time, the transistor VT1 is turned off, so the current mirror circuit is disengaged. When a pulse is applied to the clock input of D-flip-flop DD1, the direct output changes its state to "off", and inverted output - to "on". The capacitor C1 starts charging until a voltage at D-input reaches high value. The next clock pulse resets the trigger DD1 for the time of one period, and the process repeats over and over again.
Electronics and Wireless World, 1985. Vol 91, №1597