Voltage controlled oscillator circuit

Radio Magazine, 1994, N 6

A simple voltage controlled oscillator circuit described in the article of I. Bascow «Tone oscillator for Synthesizer» («Radio», 1987, N 5, p.48-50), has some drawbacks. They included a significant non-linearity control characteristic, a significant dependence of output frequency on the supply voltage and temperature. But the most important drawback is that it is hard to excite the oscillator. It happens because the high level voltage at inputs of DD1.1 and DD1.2 (see the Fig. 1 of the article mentioned above) and the low level voltage at outputs of those gates may present there simultaneously at the moment of power up. The low level voltage at inputs of the SR latch (the latch is based on DD1.3 and DD1.4 gates) sets and keeps the trigger in a state that both outputs (pins 6 and 8) have a high logic level, so the oscillator won't start.

This drawback can be eliminated by connecting gates DD1.1 and DD1.2 also as an SR latch. In this case the high logic level can not present at inputs of DD1.1 and DD1.2 in the same time, so the oscillator starts easily.

Voltage controlled oscillator circuit diagram Timing diagrams of the voltage controlled oscillator

Fig. 1
DD1 - 7400 (TTL IC); VD1, VD2 - D9B (a germanium USSR diode);
R1 = R2 = 2 KΩ; C1 = C2 = 150 pF

The circuit diagram of an oscillator with much better parameters is shown on the Fig.1, a. Gates DD1.1 and DD1.2 are connected as an SR latch. The SR latch with capacitors C1 and C2 working as an oscillator with the capacitive feedback loop. This feedback loop provides a linear relationship between the control voltage and output frequency across the operating range. The feedback reduces dependence on the supply voltage and temperature for the output frequency.

The timing diagrams of this oscillator are shown on the Fig. 1, b. After the power-up, the SR latch (DD1.3 and DD1.4) can have one of the two stable states (it has a random initial state). Let's say, the voltage at the non-inverted output of the SR latch is high, and low at the inverted output. Therefore, the only capacitor C2 can be charged (through the resistor R2), the output signal of the gate DD1.2 is linearly decreasing voltage (UB on the Fig. 1, b). When the voltage at the node "B" reaches the threshold value for the gate DD1.4, the SR latch flips to another stable state. Now the voltage at the non-inverted output is low, the capacitor C2 discharges through the Diode VD2 and the gate DD1.3.

The capacitor C1 charges the same way. As a result, the SR latch flips to the initial state, and the whole cycle repeats again.

The changing of the control voltage results in changing the charging currents for capacitors, therefore, the period of the oscillation changes. So, this is the frequency oscillator control. When the control voltage changes in range from 0 to 8 volts (R1 = R2 = 2 kOhm; C1 = C2 = 150 pF), the output frequency value is in range between 0.25 MHz and 4 MHz.

If, instead of applying Uctrl, connect resistors R1 and R2 to the power supply (5 Volts), we get an oscillator that produces square pulses on its non-inverted and inverted outputs, and the voltage at the outputs of gates DD1.1 and DD1.2 is a linearly changing voltage with low distortion (see the nodes UA and UB on the Fig. 1, b). The minimum dependence of the frequency on the supply voltage is when the resistance of both resistors R1 and R2 is about 2 kOhm. If the voltage supply changes in range from -5% to +5%, the output frequency changes between -0.1% and +0.1%. The temperature dependence is about 0.05%/°C.

Circuit diagram of the monostable multivibrator Timing diagrams of the voltage monostable multivibrator

Fig. 2
DD1 - 7400 (TTL IC); VD1 - D9B (a germanium USSR diode);
R1 - 2 KΩ; C1 - 330 pF

The method of frequency (period) control, described above, can be used to control a pulse width. A monostable multivibrator circuit diagram is shown on the Fig. 2, a, a pulse width of the output signal is controlled by the control voltage Uctrl. Let's see how the circuit operates. In the initial state, the voltage at the the non-inverted output of the SR latch is low, the voltage at the inverted output is high. Starting low-level pulses switches SR latch to a stable state with high logic level on its output. The capacitor C1 is charging. The voltage at the output of the gate DD1.1 is linearly decreases. When the voltage reaches a threshold value of the gate DD1.3, the SR latch flips to the initial state.

The feature of this multivibrator is that it can produce pulses with the width wider than the width of input pulses (t2 - t3 on the Fig.2, b). The width of output pulses depends on the resistance of R1, capacitance of C1 and the control voltage value. If the control voltage changes in range from 0 to 8 Volts (R1 = 2 kOhm; C1 = 330 pF), the width of output pulses changes in range of 5...0.2 ms.

The oscillator and multivibrator described above can be used in switched-mode power supplies, measuring instruments, synthesizers and other electronic devices.

A. Ignatenko, Yekaterinburg