This voltage controlled oscillator design is based on the CMOS integral circuit CD4011. The oscillator provides quite good linearity, its current consumption is very low. The power supply voltage can be in range from 5 to 15 Volts. The circuit can work as a frequency modulator.
The output frequency of the oscillator depends on parameters of R1, R2, C1 and the power supply voltage.
Let's see how the circuit works. The circuit includes two RS latches based on NAND gates - DD1.1, DD2.1 and DD3.1, DD4.1. If the output OUT1 is low, then the output OUT2 is high and the diode D2 is not conducting current. The logic level at the pin 1 is high, the capacitor C1 discharges. The logic level at the pin 6 changes from high to low, so logic levels at pins 4 and 3 also changing. The capacitor C1 charges in the opposite polarity (the charge current passes through protective diodes on the inputs of logic gates). The circuit produces pulses which amplitude depends on the power supply voltage, and their frequency depends on the controlling voltage source Uctrl. The middle frequency is provided if the Uctrl=0. Note, if change the polarity of diodes D1, D2, the controlling voltage Uctrl should be applied relative to the power supply voltage +U.
Voltage controlled oscillator circuit
DD1 - CD4011; D1, D2 - 1N4148;
R1, R2 - 100k; C1 - 4.7nF; C2, C3 - 0.1 μF;
±Uctrl = -1.5..3 at +U = 5 V;
+U = 5..15 V
The figure 2 shows frequency versus controlling voltage Uctrl plot, and as it seen the plot is linear. To make the controlling voltage range wider, it takes to use a higher power supply voltage of 10..15 Volts.
The upper operating frequency of the voltage controlled oscillator circuit depends on parameters of R1, R2, C1 and the integrated circuit DD1. The upper operating frequency can reach up to several MHz. The frequency vs.voltage ratio is about 360 Hz/V for the power supply voltage of 5 Volts.
The LTSpice simulation of this voltage controlled oscillator circuit can't start without some tricks because the circuit is symmetric, so it takes to introduces an imbalance into the circuit and add protective diodes (there is no protective diodes in the LTSpice models of CD4000 series). The gate DD1.1 parameter ("Spiceline") SPEED=1.0 has been changed to SPEED=2.0, and now the simulation can run.